Reference is made to FIG. 1 which illustrates a block diagram for an integrated circuit 10 including a plurality of input/output (I/O) circuits 12. The integrated circuit 10 includes a core circuit 14 which is generally speaking located at or near the center of the integrated circuit die. The I/O circuits 12 are provided surrounding the core circuit 14 in a peripheral ring. Each I/O circuit 12 may be associated with at least one input/output pad 16 of the integrated circuit 10.
It is common for the core circuit 14 to be powered at a first power supply voltage and for portions of the I/O circuits 12 to be powered at a second power supply voltage, wherein the second power supply voltage is higher than the first power supply voltage. As an example, the core circuit may be powered from a 1.2 Volt power supply while portions of the I/O circuits may be powered from a 2.5 Volt power supply. The first and second power supply voltages may be supplied external to the integrated circuit at corresponding power supply pads. Alternatively, the higher second power supply voltage may be supplied external to the integrated circuit at one or more power supply pads, while the lower first power supply voltage is generated from the higher second power supply voltage using a DC-to-DC power converter circuit provided on the integrated circuit 10.
Each I/O circuit 12 provides connectivity between the core circuit 14 and the external environment (represented by the pad 16). In accordance with that connectivity, each I/O circuit 12 implements various sub-blocks performing specific functions associated with an “input” or “output” operation.
For an “input” configured I/O circuit 12, an input buffer is coupled to the pad 16 to receive a signal from the external environment. This input buffer is designed to operate at the higher second power supply voltage. The output of the input buffer is coupled to a high-to-low level shifter circuit. This level shifter circuit is designed to operate at both the higher second power supply voltage and the lower first power supply voltage. The output of the level shifter circuit is coupled to a core interface circuit. This core interface circuit is designed to operate at the lower first power supply voltage (same as used by the core circuit) and deliver the level shifted external signal to the core circuit.
For an “output” configured I/O circuit 12, a core interface circuit is coupled to the core circuit 10 to receive a signal from the core. This core interface circuit is designed to operate at the lower first power supply voltage (same as that used by the core circuit). The output of the core interface circuit is coupled to a low-to-high level shifter circuit. This level shifter circuit is designed to operate at both the lower first power supply voltage and the higher second power supply voltage. The output of the level shifter circuit is coupled to an output buffer. This output buffer is designed to operate at the higher second power supply voltage. The pad 16 is coupled to the output of the output buffer to deliver the level shifted core signal to the external environment.
To support operation at both the lower first power supply voltage and the higher second power supply voltage, it is common for the design of the I/O circuit 12 to utilize transistors having different gate oxide thicknesses. More specifically, transistors with thinner gate oxides are used for the circuitry powered from the lower first power supply voltage, while transistors with thicker gate oxides are used for the circuitry powered from the higher second power supply voltage. As the core circuit 14 is also powered from the lower first power supply voltage, it will also typically use transistors with thinner gate oxides. In an exemplary implementation, the transistors with thinner gate oxides may be formed using a single layer gate oxide (referred to in the art as a GO1-type transistor) and the transistors with thicker gate oxides may be formed using a double layer gate oxide (referred to in the art as a GO2-type transistor).
The core interface circuits of the I/O circuit 12 are accordingly powered solely from the lower first power supply voltage and are built from single layer gate oxide (GO1) transistors. The input/output buffer circuits of the I/O circuit 12 are accordingly powered solely from the higher second power supply voltage and are built from double layer gate oxide (GO2) transistors. The level shifter circuits of the I/O circuit 12 are accordingly powered from both the lower first power supply voltage and the higher second power supply voltage and are built from a mixture of single layer gate oxide (GO1) transistors and double layer gate oxide (GO2) transistors.
For an I/O circuit 12, the single layer gate oxide (GO1) transistors (used in the core interface circuits and level shifter circuits) are positioned closer to the core circuit 14, while the double layer gate oxide (GO2) transistors (used in the buffer circuits and level shifter circuits) are positioned closer to the pad 16.
As the process technology continues to shrink, there is a corresponding decrease in the length dimension of the transistor gate. For example, gate lengths are at or approaching 20-30 nm and are expected to continue to shrink. This presents a significant photolithographic challenge to semiconductor integrated circuit fabrication. Indeed, there are recognized by those skilled in the art a number of constraints imposed on transistor layout design. One known constraint arising from decreasing transistor gate length is that the gates of the included transistors within a given block of the transistor layout must be oriented in a single critical dimension in order to achieve a tightest possible control over line width. This restriction for use of a single orientation for the transistor gates significantly adds to the complexity of designing the layout of circuitry such as the I/O circuit 12 discussed above.
As shown in FIG. 1, an I/O circuit 12 may possess a cell or block layout that is generally of a rectangular shape. The shorter edges of the layout generally face the peripheral edge of the integrated circuit 10 and the core circuit 14, respectively. The area of the integrated circuit 10 surrounding the core circuit 14 in which the I/O circuits 12 are located is generally referred to in the art as the I/O ring 18. Power supply rails (shown generally by dotted line 20) for the integrated circuit 10 are also typically positioned in the I/O ring in a manner which encircles the core circuit 14. When designing the I/O ring 18 and its included I/O circuit 12 and power supply rails 20, the layout designer must account for the fact that the cell or block layouts for the I/O circuits 12 need to be placed in both the vertical direction (as shown at the top and bottom edges of the integrated circuit 10) and the horizontal direction (as shown at the left and right edges of the integrated circuit 10).
Reference is now made to FIG. 2A which illustrates a schematic representation of the cell or block layout for a vertically oriented input/output (I/O) block 22 for the I/O circuit 12 and FIG. 2B which illustrates a schematic representation of the cell or block layout for a horizontally oriented input/output (I/O) block 42 for the I/O circuit 12. The blocks 22 and 42 each include a first rectangular section 24 in which the transistors with thicker gate oxides (GO2) powered from the higher second power supply voltage are located. Blocks 22 and 42 further include a second rectangular section 26A and 26B, respectively, in which the transistors with thinner gate oxides (GO1) powered from the lower first power supply voltage are located. It will be noted that the rectangular shape of the first section 24 is oriented perpendicular to the rectangular shape of the second sections 26A/26B. Each included transistor (GO1 or GO2) within the I/O circuit 12 has a poly gate 28 and adjacent source and drain regions 30 and 32, respectively. It will be noted that the transistors with thinner gate oxides (GO1) have a gate 28 length which is generally smaller than the gate length of the transistors with thicker gate oxides (GO2).
As a result of the photolithographic challenges described above, the transistors within a given section of the layout, and in particular within the second rectangular section 26A and 26B, must have a single orientation for the transistor gate 28. Thus, FIG. 2A shows that the transistors with thinner gate oxides (GO1) in the second rectangular section 26A are all oriented with their gate 28 widths extending in a direction perpendicular to the edge 34 (i.e., with their gate lengths extending parallel to the edge 34). The transistors with thicker gate oxides (GO2) in the first rectangular section 24 are likewise oriented in this example. Conversely, FIG. 2B shows that the transistors with thinner gate oxides (GO1) in the second rectangular section 26B are all oriented with their gate 28 widths extending in a direction parallel to the edge 34 (i.e., with their gate lengths extending perpendicular to the edge 34). The transistors with thicker gate oxides (GO2) in the first rectangular sections 24 are oriented, for example, with their gate 28 widths extending in a direction perpendicular to the edge 34 (i.e., with their gate lengths extending parallel to the edge 34).
The edge 34 of each block 22 and 42 is the edge positioned closest to the core circuit 14 (see, FIG. 1). Connectivity pins (also referred to a connectivity lines or leads) 36 are provided in the layout of the second rectangular sections 26A and 26B to make electrical connection to terminals of the included transistors with thinner gate oxides (GO1), for example, connecting to the sources/drains of the GO1 transistors in an output configured I/O circuit or connecting to the gates of the GO1 transistors in an input configured I/O circuit. These connectivity pins are provided to support an electrical connection between the core interface circuit within the I/O circuit 12 and the core circuit 14 of the integrated circuit 10. The connectivity pins 36 are accordingly oriented in a manner which extends perpendicular to the edge 34 and in the direction of the core circuit 14.
A comparison of FIG. 2A to FIG. 2B reveals that support of both a vertically oriented input/output (I/O) block 22 and a horizontally oriented input/output (I/O) block 42 for the I/O circuit 12 requires the layout designer to design two different layouts for the second rectangular sections 26A and 26B due to the limitations on gate orientation and the provision of the connectivity pins at the edge 34. More specifically, the layout designed must provide a design for the second rectangular section 26A specifically for use with a vertically oriented input/output (I/O) block 22, and provide a different design for the second rectangular section 26B specifically for use with a horizontally oriented input/output (I/O) block 42. This is not an efficient solution for integrated circuit design.
A need accordingly exists in the art for a more efficiently designed layout for integrated circuit I/O circuitry, and an in particular for a more efficiently designed and universally useful layout for the section including transistors with thinner gate oxides (GO1) that make electrically connection to core circuits.